Delegated virtualization in a multi-core processor (mcp)

ABSTRACT

The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The arrangement also enables MPEs delegate functionality to one or more groups of SPEs such that those group(s) of SPEs will act as pseudo MPEs. The pseudo MPEs will utilize pseudo virtualized control threads to control the behavior of other groups of SPEs. In a typical embodiment, the apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements.

CROSS-REFERENCE TO RELATED APPLICATION

The present invention is related in some aspects to co-pending an commonly owned application entitled Virtualization in a Multi-Core Processor (MCP) having attorney docket number END920080352US1, which was filed on Sep. 11, 2008, and assigned application Ser. No. 12/208,651, the entire contents of which are herein incorporated by reference.

FIELD OF THE INVENTION

The present invention generally relates to delegated virtualization in a (e.g., symmetric) multi-core processor (MCP). Specifically, the present invention delegates functions found in a main processing element to a group of sub-processing elements to yield a pseudo main processing element.

BACKGROUND OF THE INVENTION

Low utilization of Multi-Core Processors (MCPs) has been a major drawback of symmetric MCPs. Also, design inflexibility forces continuous leakage current in the unloaded and stand-by sub-elements, such as Sub-Processing Element (SPE), so that the power is wasted. For example, in a symmetric MCP, there can be a Main Processing Element (MPE) and 8 SPEs. In many cases, only a portion of SPEs are utilized and the overall MCP utilization is usually low. Such stand-by SPEs consume high levels of power and continuously leak. Typically, a MCP is used for the high performance digital processor scaling, but due to the complexity of the MCP design, the utilization and the efficiency of the software become challenging to optimize as the MCP dimension increases.

SUMMARY OF THE INVENTION

This disclosure describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as delegated virtualization in a (e.g., symmetric) MCP. The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The arrangement also enables MPEs to delegate functionality to one or more groups of SPEs such that those group(s) of SPEs may act as pseudo MPEs. The pseudo MPEs may utilize pseudo virtualized control threads to control the behavior of other groups of SPEs. In a typical embodiment, the apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements.

A first aspect of the present invention provides a multi-core processor, comprising: a main processing element comprising a set of virtualized control threads; a first group of sub-processing elements associated with main processing element via at least one set of virtualized control threads; and a group of sub-processing elements designated as a pseudo main processing element, the pseudo main element comprising a set of pseudo virtualized control threads.

A second aspect of the present invention provides a processing system comprising: a main processing element; a first group of sub-processing elements; a virtualized control thread associating the main processing element with the first group of sub-processing elements, the set of virtualized control threads controlling the first group of sub-processing elements; a pseudo main processing element; a second group of sub-processing elements; and a pseudo virtualized control thread associating the pseudo main processing element with the second group of sub-processing elements, the set of virtualized control threads controlling the group of sub-processing elements.

A third aspect of the present invention provides a processing method comprising: associating a main processing element with a first group of sub-processing element using a set of virtualized control threads; delegating a set of functions of the main processing element to a second group of sub-processing elements to cause the second group of sub-processing elements to act as a pseudo main processing element; associating the pseudo main processing element with a third group of sub-processing elements using a set of pseudo virtualized control threads; and controlling the first group of sub-processing elements using the set of virtualized control threads and the third group of sub-processing elements using the set of pseudo virtualized control threads.

A fourth aspect of the present invention provides a method for deploying a processing system comprising: providing a multi-core processor comprising: a main processing element comprising a set of virtualized control threads; a first group of sub-processing elements associated with main processing element via at least one of set of virtualized control threads; and a group of sub-processing elements designated as a pseudo main processing element, the pseudo main element comprising a set of pseudo virtualized control threads.

A fifth aspect of the present invention provides a computer-implemented business method comprising: associating a main processing element with a first group of sub-processing element using a set of virtualized control threads; delegating a set of functions of the main processing element to a second group of sub-processing elements to cause the second group of sub-processing elements to act as a pseudo main processing element; associating the pseudo main processing element with a third group of sub-processing elements using a set of pseudo virtualized control threads; and controlling the first group of sub-processing elements using the set of virtualized control threads and the third group of sub-processing elements using the set of pseudo virtualized control threads.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings in which:

FIG. 1 shows a related art processor.

FIG. 2 shows multi-core processor according to the present invention.

The drawings are not necessarily to scale. The drawings are merely schematic representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements.

DETAILED DESCRIPTION OF THE INVENTION

As indicated above, this disclosure describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as delegated virtualization in a (e.g., symmetric) MCP. The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The arrangement also enables MPEs delegate functionality to one or more groups of SPEs such that those group(s) of SPEs will act as pseudo MPEs. The pseudo MPEs will utilize pseudo virtualized control threads to control the behavior of other groups of SPEs. In a typical embodiment, the apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements.

Under related art systems, such as that shown in FIG. 1, the MCP 10 provides a conventional operation: a MPE 12 controls a group of SPEs 14A-N. As only a portion of SPEs are utilized, the overall MCP utilization is usually low. Moreover, stand-by SPEs 16A-N consume high levels of power and continuously leak. Typically, a MCP is used for the high performance digital processor scaling, but due to the complexity of the MCP design, the utilization and the efficiency of the software become challenging to optimize as the MCP dimension increases.

To address these issues, a configuration such as that shown in FIG. 2 is provided. As depicted, MCP 20 comprises a set of MPEs 22A-N. Each MPE 22 comprises a set of virtualized control threads V1-VN. Under the present invention MPEs 22A-N allow multiple virtualized control threads V1-VN that are each assigned to/associated with a (e.g., single or multiple) group of SPEs. For example, as further shown in FIG. 1, MCP 20 further includes groups G0-Gn of SPEs. In the example shown, group G0 comprises SPEs 26A-N, group G1 comprises SPEs 28A-N, and group Gn comprises SPEs 30A-N. It should be understood that the configuration shown is for illustrative purposes only and neither the quantity of SPEs nor their grouping is intended to limit the teachings recited herein. In any event, as can been seen, virtualized control threads V1-Vn are each associated with a specific group of SPEs. That is, virtualized control thread V1 of MPE 22A is associated with SPE group G0. In a typical embodiment, there is a one-to-one relationship between threads and groups (however, this need not be the case in that a single virtualized control thread could be associated with multiple groups). In addition, all virtualized control threads V1-Vn are shown as being embodied within a single, common MPE 22. However, it should be understood that this need not be the case. For example, virtualized control threads could be embodied in two or more different MPEs 22A-N.

Under the present invention one or more groups of SPEs could be delegated function(s) from MPE 22A-N, which would render such groups of SPEs pseudo MPEs. Examples of this are shown in FIG. 2 (after delegation has occurred). Specifically, pseudo MPEs P1-Pn are shown in FIG. 2. Each pseudo MPE has pseudo virtualized control threads PV1-n, that perform similar or identical functionality as virtualized control threads PV1-n in MPE 22A-n. Such delegation of functionality typically occurs by leveraging one or more virtualized control threads V1-n on MPE 22A.

In any event, each virtualized control thread and pseudo virtualized control thread serves to associate/link at least one MPE with at least one group of SPEs. This allows the SPEs to be controlled. Moreover, each virtualized control thread and pseudo virtualized control thread PV1-n is typically implemented as computer program code (e.g., contained on a computer readable medium). Virtualized control threads V1-n and pseudo virtualized control threads PV1-n have several functions including (among others) the following: sending program code and data to the set of groups of sub-processing elements; collecting computation results from the set of groups of sub-processing elements; sending and receiving power control requests between the set of main/pseudo processing elements and the set of groups of sub-processing element; and controlling a clock speed, power consumption and computation loading of the set of groups of sub-processing elements.

In the example shown in FIG. 2, pseudo MPE P1 is associated/linked with SPE group G1, while pseudo MPE Pn is associated/linked with SPE group Gn. Pseudo MPEs P1-Pn generally interact with and SPE control groups G1-n in a manner similar or identical to that which MPE 22A interacts with and controls group G0.

A more specific illustrative embodiment of the association of virtualized control threads with groups of SPEs will be given below:

Using the teachings recited above, each MPE and pseudo MPE allows additional virtualizations, based upon the SPEs availability and the number of requested SPEs. The MPE and pseudo MPE each keep a log of which SPEs “belong” thereto. The computation-loaded SPEs as well as unloaded & free SPEs are accounted within the log. The virtualizations are initiated by either a software or hardware request. An Operating System (OS) is designed to enable multiple independent threads with virtualization. Computer programming languages and the machine code compilers support the virtualization with libraries. The MPE and pseudo MPE also can tune the rest of the virtualized control threads and pseudo virtualized control threads using time-division resource sharing and OS-level preemptive task management to allow for multi-tasking and virtualization. By allowing main and pseudo MPEs, the MPE loading is reduced and becomes more efficient. Therefore the MCP performance vs. power efficiency increases.

As described above in conjunction with FIG. 2, groups of SPEs are assigned to the virtualized control threads, either in MPE or pseudo MPE. The MPE or pseudo MPE maintains different virtualized control threads over the SPEs, as shown in the diagram. The virtualized control threads and pseudo virtualized control threads load executable program codes and data to the SPE group, and monitor the progress and control the performance and power consumption of the SPE groups. When the SPE group produces computation results, the virtualized control threads and pseudo virtualized control threads send the results to the MPE, allowing further computations or external input/output (I/O). The number of total virtualization is limited by the MPE and SPE capacity to hold virtualization, and the number of available SPEs. Further requests for virtualization can be denied, or accepted by sharing time-division thread sharing.

The virtualized control threads and pseudo virtualized control threads control the power supply voltage and clock frequency to each SPE group (Gk), so that the active and stand-by currents are optimized for the required computations. Typically, a digital circuit speed increases when the supply voltage is raised, and the clock speed can be increased. Within the allowed supply voltage range, it is adjusted based on the computation requirements. When the loaded computation requires intensive operation, the voltage and clock frequency are raised so that it is completed within the time frame. When the loaded computation is loose and if there are plenty of time for processing, the voltage and the clock frequency are lowered to maximize performance/power ratio. An extreme case is when SPEs are standing by. The supply voltage can be reduced to 0 voltage to put the SPE is sleep mode. Slightly higher voltages can be used with a trade-off between leakage current and wake up time. It takes more time to wake an element when it is in a deeper sleep mode.

It should be understood that the present invention could be deployed on one or more computing devices (e.g., servers, clients, etc.) within a computer infrastructure. This is intended to demonstrate, among other things, that the present invention could be implemented within a network environment (e.g., the Internet, a wide area network (WAN), a local area network (LAN), a virtual private network (VPN), etc.), or on a stand-alone computer system. In the case of the former, communication throughout the network can occur via any combination of various types of communications links. For example, the communication links can comprise addressable connections that may utilize any combination of wired and/or wireless transmission methods. Where communications occur via the Internet, connectivity could be provided by conventional TCP/IP sockets-based protocol, and an Internet service provider could be used to establish connectivity to the Internet. Still yet, the computer infrastructure is intended to demonstrate that some or all of the components of such an implementation could be deployed, managed, serviced, etc. by a service provider who offers to implement, deploy, and/or perform the functions of the present invention for others.

Where computer hardware is provided, it is understood that any computers utilized will include standard elements such as a processing unit, a memory medium, a bus, and input/output (I/O) interfaces. Further, such computer systems can be in communication with external I/O devices/resources. In general, processing units execute computer program code, such as the software and functionality described above, which is stored within memory medium(s). While executing computer program code, the processing unit can read and/or write data to/from memory, I/O interfaces, etc. The bus provides a communication link between each of the components in a computer. External devices can comprise any device (e.g., keyboard, pointing device, display, etc.) that enable a user to interact with the computer system and/or any devices (e.g., network card, modem, etc.) that enable the computer to communicate with one or more other computing devices.

The hardware used to implement the present invention can comprise any specific purpose computing article of manufacture comprising hardware and/or computer program code for performing specific functions, any computing article of manufacture that comprises a combination of specific purpose and general purpose hardware/software, or the like. In each case, the program code and hardware can be created using standard programming and engineering techniques, respectively. Moreover, the processing unit therein may comprise a single processing unit, or be distributed across one or more processing units in one or more locations, e.g., on a client and server. Similarly, the memory medium can comprise any combination of various types of data storage and/or transmission media that reside at one or more physical locations. Further, the I/O interfaces can comprise any system for exchanging information with one or more external device. Still further, it is understood that one or more additional components (e.g., system software, math co-processing unit, etc.) can be included in the hardware.

While shown and described herein as delegated virtualization in a multi-core processor, it is understood that the invention further provides various alternative embodiments. For example, in one embodiment, the invention provides a computer-readable/useable medium that includes computer program code to enable a computer infrastructure to provide delegated virtualization in a multi-core processor. To this extent, the computer-readable/useable medium includes program code that implements the process(es) of the invention. It is understood that the terms computer-readable medium or computer useable medium comprises one or more of any type of physical embodiment of the program code. In particular, the computer-readable/useable medium can comprise program code embodied on one or more portable storage articles of manufacture (e.g., a compact disc, a magnetic disk, a tape, etc.), on one or more data storage portions of a computing device (e.g., a fixed disk, a read-only memory, a random access memory, a cache memory, etc.), and/or as a data signal (e.g., a propagated signal) traveling over a network (e.g., during a wired/wireless electronic distribution of the program code).

In another embodiment, the invention provides a method (e.g., business) that performs the process of the invention on a subscription, advertising, and/or fee basis. That is, a service provider, such as a Solution Integrator, could offer to provide delegated virtualization in a multi-core processor. In this case, the service provider can create, maintain, support, etc., a computer infrastructure, such as computer infrastructure that performs the process of the invention for one or more customers. In return, the service provider can receive payment from the customer(s) under a subscription and/or fee agreement and/or the service provider can receive payment from the sale of advertising content to one or more third parties.

In still another embodiment, the invention provides a processing method. In this case, a computer infrastructure can be provided and one or more systems for performing the process of the invention can be obtained (e.g., created, purchased, used, modified, etc.) and deployed to the computer infrastructure. To this extent, the deployment of a system can comprise one or more of: (1) installing program code on a computing device from a computer-readable medium; (2) adding one or more computing devices to the computer infrastructure; and (3) incorporating and/or modifying one or more existing systems of the computer infrastructure to enable the computer infrastructure to perform the process of the invention.

As used herein, it is understood that the terms “program code” and “computer program code” are synonymous and mean any expression, in any language, code or notation, of a set of instructions intended to cause a computing device having an information processing capability to perform a particular function either directly or after either or both of the following: (a) conversion to another language, code or notation; and/or (b) reproduction in a different material form. To this extent, program code can be embodied as one or more of: an application/software program, component software/a library of functions, an operating system, a basic I/O system/driver for a particular computing and/or I/O device, and the like.

A data processing system suitable for storing and/or executing program code can be provided hereunder and can include at least one processor communicatively coupled, directly or indirectly, to memory element(s) through a system bus. The memory elements can include, but are not limited to, local memory employed during actual execution of the program code, bulk storage, and cache memories that provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution. Input/output or I/O devices (including, but not limited to, keyboards, displays, pointing devices, etc.) can be coupled to the system either directly or through intervening I/O controllers.

Network adapters also may be coupled to the system to enable the data processing system to become coupled to other data processing systems, remote printers, storage devices, and/or the like, through any combination of intervening private or public networks. Illustrative network adapters include, but are not limited to, modems, cable modems and Ethernet cards.

The foregoing description of various aspects of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to a person skilled in the art are intended to be included within the scope of the invention as defined by the accompanying claims. 

1. A multi-core processor, comprising: a main processing element comprising a set of virtualized control threads; a first group of sub-processing elements associated with main processing element via at least one set of virtualized control threads; and a group of sub-processing elements designated as a pseudo main processing element, the pseudo main processing element comprising a set of pseudo virtualized control threads.
 2. The multi-core processor of claim 1, the pseudo main processing element associated with a second group of sub processing elements via the set of pseudo virtualized control threads.
 3. The multi-core processor of claim 1, the first group of sub-processing elements comprising a plurality of sub-processing elements.
 4. The multi-core processor of claim 1, the set of virtualized control threads being configured to send program code and data to the first group of sub-processing elements.
 5. The multi-core processor of claim 4, the set of virtualized control threads being further configured to collect computation results from the first group of sub-processing elements.
 6. The multi-core processor of claim 1, the set of virtualized control threads controlling a clock speed, power consumption and computation loading of the set of first group of sub-processing elements.
 7. The multi-core processor of claim 1, the set of virtualized control threads being configured to send and receive power control requests between the main processing element and the first group of sub-processing elements.
 8. The multi-core processor of claim 1, the pseudo main processing element associated with a second group of sub processing elements via the set of pseudo virtualized control threads.
 9. A processing system, comprising: a main processing element; a first group of sub-processing elements; a virtualized control thread associating the main processing element with the first group of sub-processing elements, the set of virtualized control threads controlling the first group of sub-processing elements; a pseudo main processing element; a second group of sub-processing elements; and a pseudo virtualized control thread associating the pseudo main processing element with the second group of sub-processing elements, the set of virtualized control threads controlling the group of sub-processing elements.
 10. The processing system of claim 9, the pseudo main processing element being a third group of sub-processing elements that have been delegated a set of functions from at least one of a set of main processing elements.
 11. The processing system of claim 9, the virtualized control thread and the pseudo virtualized control thread being configured to send program code and data to the first group of sub-processing elements and the second group of sub-processing elements.
 12. The processing system of claim 12, the virtualized control thread and the pseudo virtualized control thread being further configured to collect computation results from the first group of sub-processing elements and the second group of sub-processing elements.
 13. The processing system of claim 9, the virtualized control thread and the pseudo virtualized control thread controlling a clock speed, power consumption and computation loading of the first group of sub-processing elements and the second group of sub-processing elements.
 14. A processing method, comprising: associating a main processing element with a first group of sub-processing element using a set of virtualized control threads; delegating a set of functions of the main processing element to a second group of sub-processing elements to cause the second group of sub-processing elements to act as a pseudo main processing element; associating the pseudo main processing element with a third group of sub-processing elements using a set of pseudo virtualized control threads; and controlling the first group of sub-processing elements using the set of virtualized control threads and the third group of sub-processing elements using the set of pseudo virtualized control threads.
 15. The processing method of claim 14, further comprising sending program code and data to the first group of sub-processing elements via the set of virtualized control threads and to the third set of groups of sub-processing elements via the set of pseudo virtualized control threads.
 16. The processing method of claim 14, further comprising receiving computation results from the first group of sub-processing elements via the set of virtualized control threads and from the third group of sub-processing elements via the set of pseudo virtualized control threads.
 17. The processing method of claim 14, the controlling comprising controlling a clock speed, a power consumption and a computation loading of the first group of sub-processing elements and the third group of sub-processing elements.
 18. The processing method of claim 14, the set of virtualized control threads being embodied as program code within the set of main processing elements, and the set of pseudo virtualized control threads being embodied as program code within the pseudo main processing element.
 19. The processing method of claim 14, the main processing element, the first group of sub-processing elements, the set of virtualized control threads, the pseudo main processing element, the third group of sub-processing elements, and the set of pseudo virtualized control threads comprising a multi-core processor.
 20. A method for deploying a processing system, comprising: providing a multi-core processor comprising: a main processing element comprising a set of virtualized control threads; a first group of sub-processing elements associated with main processing element via at least one of set of virtualized control threads; and a group of sub-processing elements designated as a pseudo main processing element, the pseudo main element comprising a set of pseudo virtualized control threads. 